In general, a liquid crystal display (LCD) device is capable of adjusting light transmission ratios of liquid crystal cells to display image data by individually supplying data signals corresponding to the image data to the liquid crystal cells. Accordingly, the LCD device includes a liquid crystal display panel in which liquid crystal cells are aligned in a matrix configuration and a driver integrated circuit (IC).
The liquid crystal display panel includes a color filter substrate and a thin film transistor (TFT) array substrate that oppose each other and a liquid crystal layer between the color filter substrate and the TFT array substrate. The TFT array substrate includes data lines for transmitting data signals supplied from a data driver IC to the liquid crystal cells and orthogonal gate lines for transmitting scan signals supplied from a gate driver IC, wherein the liquid crystal cells are defined at intersections of the data lines and gate lines. The gate driver IC sequentially supplies scan signals to the gate lines to sequentially select liquid crystal cells on a one by one basis. In addition, the data driver IC supplies data signals to the liquid crystal cells of selected gate lines.
FIG. 1 is the top view of a conventional pixel structure. This pixel structure is called the “Cs on common” structure. This pixel structure is set on a substrate (not shown) and includes gate lines 10, a data line 11, and a thin film transistor 12. A pixel region is defined by arranging a plurality of gate lines 10 along a first direction and a plurality of data lines 11 along a second direction perpendicular to the first direction. The thin film transistor 12 includes a gate electrode 120, a channel layer 121, a source electrode 122 and a drain electrode 123. The gate electrode 120 is electrically connected to the gate line 10. The source electrode 122 is electrically connected to the data line 11. The drain 123 is electrically connected to the pixel electrode 13 through the contact window 14.
The pixel storage capacitor 16 includes a bottom electrode 15, a top electrode 17, and a dielectric layer between the bottom electrode 15 and the top electrode 17. The top electrode 17 is electrically connected to the pixel electrode 13 through the contact window 18. The bottom electrode 15 is a common line arranged in the pixel region approximately parallel to the gate line 10, and is in the first metal layer as same as the gate line 10 and the gate electrode 120. The top electrode 17, the data line 11, and the source/drain electrodes 122, 123 are formed by photographing and etching the second metal layer. A gate insulating layer (not shown) is disposed between the first metal and second metal layers. A passivation layer (not shown) is disposed between the second metal layer and the pixel electrode 13.
FIG. 2 is the top view of a conventional pixel array. In conventional pixel array, only the common lines 15 of the pixels arranged along the first direction are electrically connected. Therefore, the RC delay effect of the common line in conventional pixel array is still obvious and degrades a picture quality.